DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 215

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.3.14
BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch
destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is
cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by
a power-on reset or a manual reset. Other bits are not initialized by a power-on reset. The four
BRSR registers (eight pairs for the F-ZTAT version supporting full functions of E10A) have a
queue structure and a stored register is shifted at every branch.
Initial value:
Initial value:
Bit
31
30 to 28
27 to 0
R/W:
R/W:
Bit:
Bit:
BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9
Branch Destination Register (BRDR) (Only in F-ZTAT Version)
DVF
31
15
R
R
Bit Name
DVF

BDA27 to
BDA0
0
-
30
14
R
R
0
-
-
29
13
R
R
0
-
-
Initial
Value
0
All 0
Undefined R
28
12
R
R
0
-
-
BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16
27
11
R
R
-
-
R/W
R
R
26
10
R
R
-
-
Description
BRDR Valid Flag
Indicates whether a branch destination address is
stored. This flag bit is set to 1 when a branch occurs.
This flag is cleared to 0 when BRDR is read, the
setting to enable PC trace is made, or BRDR is
initialized by a power-on reset.
0: The value of BRDR register is invalid
1: The value of BRDR register is valid
Reserved
These bits are always read as 0. The write value
should always be 0.
Branch Destination Address
Store bits 27 to 0 of the branch destination address.
25
R
R
9
-
-
BDA8
24
R
R
8
-
-
BDA7
23
R
R
7
-
-
BDA6
Rev. 3.00 May 17, 2007 Page 157 of 1582
22
R
R
6
-
-
Section 7 User Break Controller (UBC)
BDA5
21
R
R
5
-
-
BDA4
20
R
R
4
-
-
BDA3
19
R
R
3
-
-
REJ09B0181-0300
BDA2
18
R
R
2
-
-
BDA1
17
R
R
1
-
-
BDA0
16
R
R
0
-
-