DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 521

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

11.3.5
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of
interrupt requests for each channel. The MTU2 has seven TIER registers, two for channel 0 and
one each for channels 1 to 5.
• TIER_0, TIER_1, TIER_2, TIER_3, TIER_4
Bit
0
Bit
7
Bit Name
CMPCLR5W 0
Bit Name
TTGE
Timer Interrupt Enable Register (TIER)
Initial value:
Initial
Value
Initial
Value
0
R/W:
Bit:
TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA
R/W
7
0
R/W
R/W
R/W
R/W
R/W
6
0
Description
TCNT Compare Clear 5W
Enables or disables requests to clear TCNTW_5 at
TGRW_5 compare match or input capture.
0: Disables TCNTW_5 to be cleared to H'0000 at
1: Enables TCNTW_5 to be cleared to H'0000 at
Description
A/D Converter Start Request Enable
Enables or disables generation of A/D converter start
requests by TGRA input capture/compare match.
0: A/D converter start request generation disabled
1: A/D converter start request generation enabled
R/W
5
0
TCNTW_5 and TGRW_5 compare match or input
capture
TCNTW_5 and TGRW_5 compare match or input
capture
R/W
4
0
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
3
0
Rev. 3.00 May 17, 2007 Page 463 of 1582
R/W
2
0
R/W
1
0
R/W
0
0
REJ09B0181-0300