DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 821

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Receiving Serial Data (Asynchronous Mode):
Figure 15.6 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCI for reception.
No
No
Read ORER, PER, and FER
Figure 15.6 Sample Flowchart for Receiving Serial Data (1)
Read RDRF flag in SCSSR
Clear RE bit in SCSCR to 0
PER, FER, or ORER = 1?
SCRDR, and clear RDRF
Read receive data in
flag in SCSSR to 0
All data received?
Start of reception
End of reception
flags in SCSSR
RDRF = 1?
No
Yes
Yes
Error handling
Yes
Section 15 Serial Communication Interface (SCI)
[1] Receive error handling and break
[2] SCI status check and receive data read:
[3] Serial reception continuation procedure:
detection:
PER, and FER flags in SCSSR to identify
the error. After performing the
appropriate error processing, ensure that
the ORER, PER, and FER flags are all
cleared to 0. Reception cannot be
resumed if any of these flags are set to 1.
In the case of a framing error, a break
can also be detected by reading the
value of the RXD pin.
then read the receive data in SCRDR
clear the RDRF flag to 0.
RDRF flag to 0 before the stop bit for the
current frame is received. The RDRF flag
is cleared automatically when the direct
memory access controller (DMAC) or
data transfer controller (DTC) is activated
by an RXI interrupt to read the SCRDR
value, and this step is not needed.
If a receive error occurs, read the ORER,
Read SCSSR and check that RDRF = 1,
To continue serial reception, clear the
Rev. 3.00 May 17, 2007 Page 763 of 1582
REJ09B0181-0300