DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 24

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

22.6 Port F ............................................................................................................................... 1211
Section 23 Flash Memory................................................................................ 1215
23.1 Features............................................................................................................................ 1215
23.2 Overview.......................................................................................................................... 1217
23.3 Input/Output Pins............................................................................................................. 1225
23.4 Register Descriptions....................................................................................................... 1225
23.5 On-Board Programming Mode ........................................................................................ 1252
23.6 Protection......................................................................................................................... 1271
23.7 Flash Memory Emulation in RAM .................................................................................. 1274
23.8 Usage Notes ..................................................................................................................... 1277
23.9 Supplementary Information ............................................................................................. 1283
23.10 Programmer Mode ........................................................................................................... 1321
Rev. 3.00 May 17, 2007 Page xxiv of lviii
22.5.3 Port E Port Registers H and L (PEPRH and PEPRL) ......................................... 1207
22.6.1 Register Descriptions.......................................................................................... 1212
22.6.2 Port F Data Register L (PFDRL) ........................................................................ 1212
23.2.1 Block Diagram.................................................................................................... 1217
23.2.2 Operating Mode .................................................................................................. 1218
23.2.3 Mode Comparison .............................................................................................. 1220
23.2.4 Flash Memory Configuration.............................................................................. 1221
23.2.5 Block Division .................................................................................................... 1222
23.2.6 Programming/Erasing Interface .......................................................................... 1223
23.4.1 Registers ............................................................................................................. 1225
23.4.2 Programming/Erasing Interface Registers .......................................................... 1228
23.4.3 Programming/Erasing Interface Parameters ....................................................... 1235
23.4.4 RAM Emulation Register (RAMER).................................................................. 1250
23.5.1 Boot Mode .......................................................................................................... 1252
23.5.2 User Program Mode............................................................................................ 1256
23.5.3 User Boot Mode.................................................................................................. 1266
23.6.1 Hardware Protection ........................................................................................... 1271
23.6.2 Software Protection ............................................................................................ 1272
23.6.3 Error Protection .................................................................................................. 1272
23.8.1 Switching between User MAT and User Boot MAT.......................................... 1277
23.8.2 Interrupts during Programming/Erasing ............................................................. 1278
23.8.3 Other Notes......................................................................................................... 1281
23.9.1 Specifications of the Standard Serial Communications Interface
23.9.2 Areas for Storage of the Procedural Program and Data for Programming.......... 1313
in Boot Mode ...................................................................................................... 1283