DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 997

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18.5
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun error. Table 18.4 shows the
contents of each interrupt request.
Table 18.4 Interrupt Requests
When the interrupt condition described in table 18.4 is 1, the CPU executes an interrupt exception
handling. Interrupt sources should be cleared in the exception handling. The TDRE and TEND
bits are automatically cleared to 0 by writing the transmit data to ICDRT. The RDRF bit is
automatically cleared to 0 by reading ICDRR. The TDRE bit is set to 1 again at the same time
when the transmit data is written to ICDRT. Therefore, when the TDRE bit is cleared to 0, then an
excessive data of one byte may be transmitted. The TDRE, TEND, and RDRF bits are
automatically cleared while the specified number of transfers by the DTC is in progress; however,
the TDRE, TEND, and RDRF bits are not cleared automatically when the transfer is complete.
Interrupt Request
Transmit data Empty IITXI
Transmit end
Receive data full
STOP recognition
NACK receive
Arbitration lost/
overrun error
I
2
C2 Interrupt Sources
Abbreviation Interrupt Condition
IITEI
IIRXI
IISTPI
IINAKI
(TDRE=1)
(TEND=1)
(RDRF=1)
(STOP=1)
{(NACKF=1)+(AL=1)}
(NAKIE=1)
•
•
•
•
(STIE=1)
(TIE=1)
(TEIE=1)
(RIE=1)
•
Rev. 3.00 May 17, 2007 Page 939 of 1582
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Section 18 I
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C Bus Interface 2 (I
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