DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 280

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus State Controller (BSC)
9.3
9.3.1
In the architecture, this LSI has 32-bit address spaces.
As listed in tables 9.2 to 9.15, this LSI can connect nine areas to each type of memory, and it
outputs chip select signals (CS0 to CS8) for each of them. CS0 is asserted during area 0 access. In
access to SDRAM connected to areas 2 and 3, signals such as RASx, CASx, RD/WR, and
DQMxx will be asserted. Furthermore, when the PCMCIA interface is selected in areas 5 and 6,
CE1A, CE1B, CE2A, and CE2B as well as CS5 and CS6 are asserted, according to the bytes to be
accessed.
9.3.2
The external address space has a capacity of 1.5 Gbytes and is used by dividing into 9 spaces. The
memory to be connected and the data bus width are specified in each space. The address map for
the entire address space is listed in tables 9.2 to 9.15.
Table 9.2
Rev. 3.00 May 17, 2007 Page 222 of 1582
REJ09B0181-0300
Address
H'00000000 to
H'0003FFFF
H'00040000 to
H'01FFFFFF
H'02000000 to
H'03FFFFFF
H'04000000 to
H'0BFFFFFF
H'0C000000 to
H'0DFFFFFF
Area Overview
Area Division
Address Map
Address Map: SH7083 (256-Kbyte Flash Memory Version) in On-Chip ROM-
Enabled Mode
Area
On-chip ROM
Reserved
CS0 space
Reserved
CS3 space
Memory Type
Normal space
SRAM with byte selection
Burst ROM (asynchronous)
Burst ROM (synchronous)
Normal space
SRAM with byte selection
SDRAM
Capacity
256 Kbytes
32 Mbytes
32 Mbytes
Bus
Width
32 bits
8 or 16
bits*
8 or 16
bits*

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