DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1040

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 20 Compare Match Timer (CMT)
20.5
20.5.1
The CMT operation can be disabled or enabled using the standby control register. The initial
setting is for CMT operation to be halted. Access to a register is enabled by clearing module
standby mode. For details, refer to section 26, Power-Down Modes.
20.5.2
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 20.5 shows
the timing to clear the CMCNT counter.
Rev. 3.00 May 17, 2007 Page 982 of 1582
REJ09B0181-0300
Figure 20.5 Conflict between Write and Compare-Match Processes of CMCNT
Usage Notes
Module Standby Mode Setting
Conflict between Write and Compare-Match Processes of CMCNT
Peripheral operating
Counter clear
Internal write
clock (Pφ)
Address
CMCNT
CMCSR write cycle
N
T1
CMCNT
T2
H'0000

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