DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 790

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 15 Serial Communication Interface (SCI)
Rev. 3.00 May 17, 2007 Page 732 of 1582
REJ09B0181-0300
Bit
5
4
3
Bit Name
TE
RE
MPIE
Initial
value
0
0
0
R/W
R/W
R/W
R/W
Description
Transmit Enable
Enables or disables the SCI serial transmitter.
0: Transmitter disabled*
1: Transmitter enabled*
Notes: 1. The TDRE flag in SCSSR is fixed at 1.
Receive Enable
Enables or disables the SCI serial receiver.
0: Receiver disabled*
1: Receiver enabled*
Notes: 1. Clearing RE to 0 does not affect the receive
Multiprocessor Interrupt Enable (only when MP = 1 in
SCSMR in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped and setting of the
RDRF, FER, and ORER status flags in SCSSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
to 0 and normal receiving operation is resumed. For
details, refer to section 15.4.4, Multiprocessor
Communication Function.
2. Serial transmission starts after writing
2. Serial reception starts when a start bit is
flags (RDRF, FER, PER, and ORER). These
flags retain their previous values.
detected in asynchronous mode, or
synchronous clock input is detected in clock
synchronous mode. Select the receive
format in SCSMR before setting RE to 1.
transmit data into SCTDR and clearing the
TDRE flag in SCSSR to 0 while the
transmitter is enabled. Select the transmit
format in the serial mode register (SCSMR)
before setting TE to 1.
2
1
2
1