DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1024

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 19 A/D Converter (ADC)
19.4.5
The A/D converter can be independently activated by an A/D conversion request from the interval
timer of the MTU2 or MTU2S.
To activate the A/D converter by the MTU2 or MTU2S, first set the TRGE bit in the A/D
control/status register (ADCSR) to 1, and then set the A/D trigger select register (ADTSR). After
this register setting has been made, the ADST bit in ADCR is automatically set to 1 when an A/D
conversion request from the interval timer of the MTU2 or MTU2S occurs. The timing from
setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to the
ADST bit by software.
19.4.6
A/D conversion can be externally triggered. When the TRGE bit in the A/D control/status register
(ADCSR) is set to 1 while the A/D trigger select registers_0 and _1 (ADTSR_0 and ADSTR_1)
are set to external trigger pin input, external trigger input is enabled at the ADTRG pin. A falling
edge of the ADTRG pin sets the ADST bit to 1 in ADCR, starting A/D conversion. Other
operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by
software. Figure 19.3 shows the timing.
Rev. 3.00 May 17, 2007 Page 966 of 1582
REJ09B0181-0300
CK
ADTRG
External trigger
signal
ADST
A/D Converter Activation by MTU2 or MTU2S
External Trigger Input Timing
Figure 19.3 External Trigger Input Timing
A/D conversion