DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 895

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Figure 16.5 shows an example of the operation for transmission.
4. When modem control is enabled, transmission can be stopped and restarted in accordance with
the CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the
mark state after transmission of one frame. When CTS is set to 0, the next transmit data is
output starting from the start bit.
Figure 16.6 shows an example of the operation when modem control is used.
Serial data
Serial
data
TDFE
TEND
TXD
CTS
1
TXIF interrupt
request
Figure 16.6 Example of Operation Using Modem Control (CTS)
Start
bit
0
Start
bit
Data written to SCFTDR
and TDFE flag read as 1
then cleared to 0 by TXIF
interrupt handler
0
D0
D0
Figure 16.5 Example of Transmit Operation
D1
One frame
D1
Data
(8-Bit Data, Parity, One Stop Bit)
D7
D7 0/1
Drive high before stop bit
Parity
bit
Parity
bit
0/1
TXIF interrupt
request
Stop
bit
Section 16 Serial Communication Interface with FIFO (SCIF)
Stop
bit
1
Start
bit
0
D0
D1
Rev. 3.00 May 17, 2007 Page 837 of 1582
Data
Start
bit
0
D7
D0 D1
Parity
bit
0/1
Stop
bit
1
D7 0/1
Idle state
(mark state)
REJ09B0181-0300
1