DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1035

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

20.2.1
CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is
stopped.
Initial value:
20.2.2
CMCSR is a 16-bit register that indicates compare match generation, enables interrupts and selects
the counter input clock.
Initial value:
Bit
15 to 2
1
0
Note:
R/W:
R/W:
Bit:
Bit:
1.
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Compare Match Timer Start Register (CMSTR)
Compare Match Timer Control/Status Register (CMCSR)
15
15
R
R
0
0
-
-
Bit Name

STR1
STR0
14
14
R
R
0
0
-
-
13
13
R
R
0
0
-
-
Initial
value
All 0
0
0
12
12
R
R
0
0
-
-
11
11
R
R
0
0
-
-
R/W
R
R/W
R/W
10
10
R
R
0
0
-
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Count Start 1
Specifies whether compare match counter 1 operates
or is stopped.
0: CMCNT_1 count is stopped
1: CMCNT_1 count is started
Count Start 0
Specifies whether compare match counter 0 operates
or is stopped.
0: CMCNT_0 count is stopped
1: CMCNT_0 count is started
R
R
9
0
9
0
-
-
R
R
8
0
8
0
-
-
(R/W)*
CMF
R
7
0
7
0
-
1
CMIE
R/W
Rev. 3.00 May 17, 2007 Page 977 of 1582
R
6
0
6
0
Section 20 Compare Match Timer (CMT)
-
R
R
5
0
5
0
-
-
R
R
4
0
4
0
-
-
R
R
3
0
3
0
-
-
REJ09B0181-0300
R
R
2
0
2
0
-
-
STR1
R/W
R/W
1
0
1
0
CKS[1:0]
STR0
R/W
R/W
0
0
0
0