DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 795

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
4
Bit Name
FER
Initial
value
0
R/W
R/(W)* Framing Error
Description
Indicates that a framing error occurred during data
reception in asynchronous mode, causing abnormal
termination.
0: Indicates that reception is in progress or was
[Clearing conditions]
•
•
1: Indicates that a framing error occurred during
[Setting condition]
•
Notes: 1. The FER flag is not affected and retains
completed successfully*
reception
By a power-on reset or in standby mode
When 0 is written to FER after reading FER = 1
When the SCI founds that the stop bit at the end
of the received data is 0 after completing
reception*
2. In 2-stop-bit mode, only the first stop bit is
Section 15 Serial Communication Interface (SCI)
its previous value when the RE bit in
SCSCR is cleared to 0.
checked for a value to 1; the second stop
bit is not checked. If a framing error
occurs, the receive data is transferred to
SCRDR but the RDRF flag is not set.
Subsequent serial reception cannot be
continued while the FER flag is set to 1.
2
Rev. 3.00 May 17, 2007 Page 737 of 1582
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REJ09B0181-0300