DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 994

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 18 I
Rev. 3.00 May 17, 2007 Page 936 of 1582
REJ09B0181-0300
No
No
No
Clear ACKBT in ICIER to 0
Clear RCVD in ICCR1 to 0
Set ACKBT in ICIER to 1
Clear MST in ICCR1 to 0
Clear TRS in ICCR1 to 0
Set RCVD in ICCR1 to 1
2
Clear TEND in ICSR
Clear TDRE in ICSR
Dummy-read ICDRR
Read RDRF in ICSR
Read RDRF in ICSR
Read STOP in ICSR
Mater receive mode
Clear STOP in ICSR
C Bus Interface 2 (I
Write 0 to BBSY
Read ICDRR
Read ICDRR
Read ICDRR
Last receive
RDRF=1 ?
RDRF=1 ?
STOP=1 ?
and SCP
End
- 1?
Figure 18.19 Sample Flowchart for Master Receive Mode
Yes
Yes
Yes
No
Yes
2
C2)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear the STOP flag.
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[14] Clear RCVD.
[15] Set slave receive mode.
Notes: * Make sure that no interrupt will be generated during steps [1] to [3].
Clear TEND, select master receive mode, and then clear TDRE. *
Set acknowledge to the transmit device. *
Dummy-read ICDDR. *
Wait for 1 byte to be received
Check whether it is the (last receive - 1).
Read the receive data.
Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
Read the (final byte - 1) of received data.
Wait for the last byte to be receive.
When the size of receive data is only one byte in reception,
The step [8] is dummy-read in ICDRR.
steps [2] to [6] are skipped after step [1], before jumping to step [7].
However, when the size of receive data is two bytes and more,
steps [2] to [6] are not skipped after step [1].