DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 427

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 9.34 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single
Transfer from the SDRAM interface to the external device with DACK
Notes: DMAC is driven by Bφ. The minimum number of idle cycles is not affected by changing a
CS3BCR Idle Setting
0
0
0
0
1
1
1
1
2
2
2
2
4
4
4
4
clock ratio.
*
Other than the following cases.
Single address mode transfer from the external device with DACK to the SDRAM
interface, where the minimum number of idle cycles is not affected by the IWW,
IWRWD, IWRWS, IWRRD, and IWRRS bits in CSnBCR.
CMNCR.DMAIWA = 0, where the setting is identical to CMNCR.DMAIW[1:0] in table
9.33.
Address Mode for the SDRAM Interface (2)
BSC Register Setting*
CS3WCR.WTRP Setting
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
Rev. 3.00 May 17, 2007 Page 369 of 1582
Section 9 Bus State Controller (BSC)
Minimum Number of
Idle Cycles
3
3
3
4
3
3
3
4
3
3
3
4
5
5
5
5
REJ09B0181-0300

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