DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 389

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Refreshing: This LSI has a function for controlling SDRAM refreshing. Auto-refreshing can be
performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous
refreshing can be performed by setting the RRC[2:0] bits in RTCSR. If SDRAM is not accessed
for a long period, self-refresh mode, in which the power consumption is low, can be activated by
setting both the RMODE bit and the RFSH bit to 1.
1. Auto-refreshing
The number of refreshings set by bits RRC[2:0] in RTCSR is performed at intervals
determined by the input clock selected by bits CKS[2:0] in RTCSR, and the value set in
RTCOR. Register settings should be made so as to satisfy the refresh interval stipulation for
the SDRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH
bits in SDCR, then make the CKS[2:0] and RRC[2:0] settings. When the clock is selected by
bits CKS[2:0], RTCNT starts counting up from the value at that time. The RTCNT value is
constantly compared with the RTCOR value, and if the two values are the same, a refresh
request is generated and an auto-refresh is performed for the number of times specified by the
RRC[2:0]. At the same time, RTCNT is cleared to 0 and the count-up is restarted.
Figure 9.28 shows the auto-refresh cycle timing. After starting auto-refreshing, PALL
command is issued in the Tp cycle to make all the banks to precharged state from active state
when some bank is being precharged. Then REF command is issued in the Trr cycle after
inserting idle cycles of which number is specified by the WTRP[1:0] bits in CS3WCR. A new
command is not issued for the duration of the number of cycles specified by the WTRC[1:0]
bits in CS3WCR after the Trr cycle. The WTRC[1:0] bits must be set so as to satisfy the
SDRAM refreshing cycle time stipulation (tRC). An idle cycle is inserted between the Tp
cycle and Trr cycle when the setting value of the WTRP[1:0] bits in CS3WCR is one cycle or
more.
Rev. 3.00 May 17, 2007 Page 331 of 1582
Section 9 Bus State Controller (BSC)
REJ09B0181-0300