DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 853

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
7
6
5
Bit Name
C/A
CHR
PE
Initial
value
0
0
0
R/W
R/W
R/W
R/W
Description
Communication Mode
Selects whether the SCIF operates in asynchronous or
clock synchronous mode.
0: Asynchronous mode
1: Clock synchronous mode
Character Length
Selects 7-bit or 8-bit data in asynchronous mode. In the
clock synchronous mode, the data length is always
eight bits, regardless of the CHR setting.
0: 8-bit data
1: 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of
Parity Enable
Selects whether to add a parity bit to transmit data and
to check the parity of receive data, in asynchronous
mode. In clock synchronous mode, a parity bit is neither
added nor checked, regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked*
Note: * When PE is set to 1, an even or odd parity bit
Section 16 Serial Communication Interface with FIFO (SCIF)
the transmit FIFO data register is not
transmitted.
is added to transmit data, depending on the
parity mode (O/E) setting. Receive data parity
is checked according to the even/odd (O/E)
mode setting.
Rev. 3.00 May 17, 2007 Page 795 of 1582
REJ09B0181-0300