DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 156

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 5 Exception Handling
5.5.3
An instruction placed immediately after a delayed branch instruction is called "instruction placed
in a delay slot". When the instruction placed in the delay slot is an undefined code, illegal slot
exception handling starts after the undefined code is decoded. Illegal slot exception handling also
starts when an instruction that changes the program counter (PC) value is placed in a delay slot
and the instruction is decoded. The CPU handles an illegal slot instruction as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the
3. The start address of the exception handling routine is fetched from the exception handling
5.5.4
When an undefined code placed anywhere other than immediately after a delayed branch
instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts.
The CPU handles the general illegal instructions in the same procedures as in the illegal slot
instructions. Unlike processing of illegal slot instructions, however, the program counter value that
is stacked is the start address of the undefined code.
Rev. 3.00 May 17, 2007 Page 98 of 1582
REJ09B0181-0300
delayed branch instruction immediately before the undefined code or the instruction that
rewrites the PC.
vector table that corresponds to the exception that occurred. Program execution branches to
that address and the program starts. This branch is not a delayed branch.
Illegal Slot Instructions
General Illegal Instructions