DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1602

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Rev. 3.00 May 17, 2007 Page 1544 of 1582
REJ09B0181-0300
Item
7.3.10 Break Bus Cycle Register
B (BBRB)
7.3.13 Branch Source Register
(BRSR) (Only in F-ZTAT Version)
7.3.14 Branch Destination
Register (BRDR) (Only in F-ZTAT
Version)
Page Revision (See Manual for Details)
148,
149
156
157
Amended
Note: * These bits are reserved in the mask ROM and
Amended
…. This flag bit is cleared to 0 when BRSR is read, the
setting to enable PC trace is made, or BRSR is
initialized by a power-on reset or a manual reset. Other
bits are not initialized by a power-on reset. The four
BRSR registers (eight pairs for the F-ZTAT version
supporting full functions of E10A) have a queue
structure and a stored register is shifted at every
branch.
Amended
…. This flag bit is cleared to 0 when BRDR is read, the
setting to enable PC trace is made, or BRDR is
initialized by a power-on reset or a manual reset. Other
bits are not initialized by a power-on reset. The four
BRSR registers (eight pairs for the F-ZTAT version
supporting full functions of E10A) have a queue
structure and a stored register is shifted at every
branch.
Bit
10
9
8
7
6
5
4
3
2
1
0
Bit Name
CPB2*
CPB1*
CPB0*
CDB1*
CDB0
IDB1*
IDB0
RWB1*
RWB0
SZB1*
SZB0*
ROM-less versions. These bits are always read
as 0. The write value should always be 0.
Description
Bus Master Select B for I Bus
L Bus Cycle/I Bus Cycle Select B
Instruction Fetch/Data Access
Select B
Read/Write Select B
Operand Size Select B