DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 826

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 15 Serial Communication Interface (SCI)
Figure 15.9 shows a sample flowchart for initializing the SCI.
Rev. 3.00 May 17, 2007 Page 768 of 1582
REJ09B0181-0300
Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to
Set the PFC for the external pins to be
Set the RIE, TIE, TEIE, and MPIE bits
Set CKE1 and CKE0 bits in SCSCR
Set TE and RE bits of SCSCR to 1
TE and RE bits in SCSCR to 0*
Clear RIE, TIE, TEIE, MPIE,
Set data transfer format in
used (SCK, TXD, RXD)
0 or set to 1 simultaneously.
(TE and RE bits are 0)
1-bit interval elapsed?
Set value in SCBRR
Start initialization
<Transfer starts>
in SCSCR
SCSMR
Figure 15.9 Sample Flowchart for SCI Initialization
Yes
Wait
No
[4]
[5]
[2]
[3]
[1]
[1]
[2]
[3]
[4]
[5]
Set the clock selection in SCSCR.
Set the data transfer format in SCSMR.
Write a value corresponding to the bit rate to
SCBRR. Not necessary if an external clock is
used.
Set PFC of the external pin used. Set RXD
input during receiving and TXD output during
transmitting. Set SCK input/output according
to contents set by CKE1 and CKE0.
Set the TE bit or RE bit in SCR to 1.* Also
make settings of the RIE, TIE, TEIE, and
MPIE bits. At this time, the TXD, RXD, and
SCK pins are ready to be used. The TXD pin
is in a mark state during transmitting. When
synchronous clock output (clock master) is
set during receiving in clock synchronous
mode, outputting clocks from the SCK pin
starts.