DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 848

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
• Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and
• The transmit FIFO data empty and receive FIFO data full requests can activate the data
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
• In asynchronous, on-chip modem control functions (RTS and CTS).
• The number of data in the transmit and receive FIFO registers and the number of receive errors
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Figure 16.1 shows a block diagram of the SCIF.
Rev. 3.00 May 17, 2007 Page 790 of 1582
REJ09B0181-0300
receive-error interrupts are requested independently.
transfer controller (DTC) for data transfer.
power.
of the receive data in the receive FIFO register can be ascertained.
RXD3
SCK3
TXD3
CTS3
RTS3
[Legend]
SCRSR:
SCFRDR:
SCTSR:
SCFTDR:
SCSMR:
SCSCR:
Receive shift register
Receive FIFO data register
Transmit shift register
Transmit FIFO data register
Serial mode register
Serial control register
(16 stage)
SCFRDR
SCRSR
Figure 16.1 Block Diagram of SCIF
Parity check
Parity generation
(16 stage)
SCFTDR
SCTSR
Module data bus
SCFSR:
SCBRR:
SCSPTR:
SCFCR:
SCFDR:
SCLSR:
Transmission/
reception
control
Serial status register
Bit rate register
Serial port register
FIFO control register
FIFO data count register
Line status register
SCSPTR
SCSMR
SCLSR
SCFSR
SCFDR
SCFCR
SCSCR
External clock
Clock
Baud rate
generator
SCIF
SCBRRn
Pφ
Pφ/4
Pφ/16
Pφ/64
TXIF
RXIF
ERIF
BRIF
Internal
data bus