DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 888

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.13 SCSMR Settings and SCIF Communication Formats
[Legend]
x:
Table 16.14 SCSMR and SCSCR Settings and SCIF Clock Source Selection
[Legend]
x:
Rev. 3.00 May 17, 2007 Page 830 of 1582
REJ09B0181-0300
Bit 7
C/A
0
1
SCSMR SCSCR Settings
Bit 7
C/A
0
1
SCSMR Settings
Bit 6
CHR
0
1
x
Don't care
Don't care
Bit 1
CKE1
0
1
0
1
Bit 5
PE
0
1
0
1
x
Bit 0
CKE0
0
1
0
1
x
0
1
Bit 3
STOP Mode
1
0
1
0
1
0
1
x
0
Asynchronous
Clock
synchronous
Mode
Asynchronous Internal
Clock
synchronous
Clock
Source
External
Internal
External
Data Length
8-bit
7-bit
8-bit
SCK Pin Function
SCIF does not use the SCK pin. The state
of the SCK pin depends on both the SCKIO
and SCKDT bits.
Clock with a frequency 16 times the bit rate
is output.
Input a clock with frequency 16 times the
bit rate.
Setting prohibited.
Serial clock is output.
Input the serial clock.
Setting prohibited.
SCIF Transmit/Receive Clock
SCIF Communication Format
Parity Bit
Not set
Set
Not set
Set
Not set
Stop Bit Length
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
None

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