DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 745

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit
5, 4
3, 2
1, 0
2. Can be modified only once after a power-on reset.
Bit Name
POE2M[1:0] 00
POE1M[1:0] 00
POE0M[1:0] 00
Initial
value
R/W
R/W*
R/W*
R/W*
2
2
2
Description
POE2 mode 1, 0
These bits select the input mode of the POE2 pin.
00: Accept request on falling edge of POE2 input
01: Accept request when POE2 input has been sampled
10: Accept request when POE2 input has been sampled
11: Accept request when POE2 input has been sampled
POE1 mode 1, 0
These bits select the input mode of the POE1 pin.
00: Accept request on falling edge of POE1 input
01: Accept request when POE1 input has been sampled
10: Accept request when POE1 input has been sampled
11: Accept request when POE1 input has been sampled
POE0 mode 1, 0
These bits select the input mode of the POE0 pin.
00: Accept request on falling edge of POE0 input
01: Accept request when POE0 input has been sampled
10: Accept request when POE0 input has been sampled
11: Accept request when POE0 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
for 16 Pφ/16 clock pulses and all are low level.
for 16 Pφ/128 clock pulses and all are low level.
for 16 Pφ/8 clock pulses and all are low level.
for 16 Pφ/16 clock pulses and all are low level.
for 16 Pφ/128 clock pulses and all are low level.
for 16 Pφ/8 clock pulses and all are low level.
for 16 Pφ/16 clock pulses and all are low level.
for 16 Pφ/128 clock pulses and all are low level.
Rev. 3.00 May 17, 2007 Page 687 of 1582
Section 13 Port Output Enable (POE)
REJ09B0181-0300