DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 339

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
11
10
Bit Name
DTBST
DTSA
Initial
Value
0
0
R/W
R/W
R/W
transfer takes up only 3 longwords.
Description
DTC Burst Enable
Selects whether or not the DTC retains the bus
mastership and remains continuously active until all
transfer operations are complete when multiple DTC
activation requests have been generated.
0: Release the bus on the completion of transfer for each
1: Keep the DTC continuously active, i.e. only release
Notes: When this bit is set to 1, the following restrictions
DTC Short Address Mode
In this mode, the information that specifies a DTC
0: Each transfer information is read out as 4 longwords.
1: Each transfer information is read out as 3 longwords.
Note: Transfer in short-address mode is only available
individual DTC activation source.
the bus on completion of processing for all DTC
activation sources.
The transfer information are arranged as shown in
figure 8.2 (normal address mode).
The transfer information are arranged as shown in
figure 8.2 (short-address mode).
between on-chip peripheral modules and on-chip
RAM, because the higher-order 8 bits of the SAR
and DAR are considered to be all 1.
apply.
1. Clock setting with the frequency control register
2. The vector information must be in on-chip ROM
3. The transfer information must be in on-chip
4. Transfer must be between the on-chip RAM
(FRQCR) must be Iφ: Bφ: Pφ: MIφ: MPφ: = 8: 4:
4: 4: 4, 4: 2: 2: 2: 2, or 2: 1: 1: 1: 1
or on-chip RAM.
RAM.
and an on-chip peripheral module or between
external memory and an on-chip peripheral
module.
Rev. 3.00 May 17, 2007 Page 281 of 1582
Section 9 Bus State Controller (BSC)
REJ09B0181-0300