DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 917

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

This LSI has an independent synchronous serial communication unit (SSU) channel. The SSU has
master mode in which this LSI outputs clocks as a master device for synchronous serial
communication and slave mode in which clocks are input from an external device for synchronous
serial communication. Synchronous serial communication can be performed with devices having
different clock polarity and clock phase.
17.1
• Choice of SSU mode and clock synchronous mode
• Choice of master mode and slave mode
• Choice of standard mode and bidirectional mode
• Synchronous serial communication with devices with different clock polarity and clock phase
• Choice of 8/16/32-bit width of transmit/receive data
• Full-duplex communication capability
• Consecutive serial communication
• Choice of LSB-first or MSB-first transfer
• Choice of a clock source
• Five interrupt sources
• Module standby mode can be set
SCISSU0A_000120020900
Section 17 Synchronous Serial Communication Unit (SSU)
The shift register is incorporated, enabling transmission and reception to be executed
simultaneously.
Pφ/4, Pφ/8, Pφ/16, Pφ/32, Pφ/64, Pφ/128, Pφ/256, or an external clock
Transmit end, transmit data register empty, receive data full, overrun error, and conflict error.
The data transfer controller (DTC) can be activated by a transmit data register empty request or
a receive data full request to transfer data.
Features
Section 17 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 May 17, 2007 Page 859 of 1582
REJ09B0181-0300