DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1336

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 23 Flash Memory
23.8.2
(1) Download of On-Chip Program
(1.1) VBR setting change
(1.2) SCO download request and interrupt request
Rev. 3.00 May 17, 2007 Page 1278 of 1582
REJ09B0181-0300
Before downloading the on-chip program, VBR must be set to H'84000000. If VBR is set to a
value other than H'84000000, the interrupt vector table is placed in the user MAT (FMATS is
not H'AA) or the user boot MAT (FMATS is H'AA) on setting H'84000000 to VBR.
When VBR setting change conflicts with interrupt occurrence, whether the vector table before
or after VBR is changed is referenced may cause an error.
Therefore, for cases where VBR setting change may conflict with interrupt occurrence, prepare
a vector table to be referenced when VBR is H'00000000 (initial value) at the start of the user
MAT or user boot MAT.
Download of the on-chip programming/erasing program that is initiated by setting the SCO bit
in FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover.
Operation when the SCO download request and interrupt request conflicts is described below.
1. Contention between SCO download request and interrupt request
Figure 23.21 shows the timing of contention between execution of the instruction that sets
the SCO bit in FCCS to 1 and interrupt acceptance.
Interrupts during Programming/Erasing
Figure 23.20 Switching between User MAT and User Boot MAT
<User MAT>
Procedure for switching to the user boot MAT
(1) Mask interrupts.
(2) Write H'AA to FMATS.
(3) Execute four NOP instructions before
Procedure for switching to the user MAT
(1) Mask interrupts.
(2) Write a value other than H'AA to FMATS.
(3) Execute four NOP instructions before accessing
accessing the user boot MAT.
the user MAT.
<On-chip RAM>
switching to the
user boot MAT
Procedure for
Procedure for
the user MAT
switching to
<User boot MAT>