DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 434

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Acceptance of mastership for the DMAC in bus arbitration takes 1Bφ, so a NOP 1Bφ in duration is
inserted on the I bus.
Acceptance of mastership for the DTC in bus arbitration does not require the insertion of a NOP,
so bus access proceeds continuously.
9.5.14
(1)
The bus state controller (BSC) can be initialized completely only at a power-on reset. At a power-
on reset, all signals are negated and output buffers are turned off regardless of the bus cycle state.
All control registers are initialized.
In standby, sleep, and manual reset, control registers of the bus state controller are not initialized.
At a manual reset, the current bus cycle being executed is completed and then the access wait state
is entered. If a 16-byte transfer is performed by the DMAC is executed, the current access is
cancelled in longword units because the access request is cancelled by the bus master at a manual
reset. Since the RTCNT continues counting up during manual reset signal assertion, a refresh
request occurs to initiate the refresh cycle. However, a bus arbitration request by the BREQ signal
cannot be accepted during manual reset signal assertion.
(2)
There are three types of LSI internal buses: L bus, I bus, and peripheral bus. The CPU is
connected to the L bus. The DMAC, DTC, and bus state controller are connected to the I bus.
Low-speed peripheral modules are connected to the peripheral bus. On-chip memories are
connected bidirectionally to the L bus and I bus.
For an access of an external space or an on-chip peripheral module, the access is initiated via the I
bus. Thus, the DMAC and DTC can be activated without bus arbitration with the CPU while the
CPU is accessing an on-chip memory.
Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an
access via the I bus before the previous external bus cycle is completed in a write cycle. If the on-
chip peripheral module is read or written after the external low-speed memory is written, the on-
chip peripheral module can be accessed before the completion of the external low-speed memory
write cycle.
In read cycles, the CPU is placed in the wait state until read operation has been completed. To
continue the process after the data write to the device has been completed, perform a dummy read
to the same address to check for completion of the write before the next process to be executed.
Rev. 3.00 May 17, 2007 Page 376 of 1582
REJ09B0181-0300
Reset
Access in View of LSI Internal Bus Master
Others