DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 65

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

1.2
The block diagram of this LSI is shown in figure 1.1.
[Legend]
ROM:
RAM:
UBC:
AUD:
H-UDI:
INTC:
CPG:
WDT:
CPU:
BSC:
DMAC:
Notes: 1. Only in F-ZTAT version
(PFC)
port
I/O
Block Diagram
2. Only in F-ZTAT version supporting full functions of E10A
On-chip ROM
User break controller
Advanced user debugger
Central processing unit
Bus state controller
Direct memory access controller
Clock pulse generator
On-chip RAM
User debugging interface
Watchdog timer
Interrupt controller
SCI
SCIF
CMT
External bus
BSC
H-UDI
*
1
ROM
SH2
CPU
Figure 1.1 Block Diagram
INTC
Peripheral bus
controller
Power-
control
mode
down
UBC
RAM
DTC:
PFC:
MTU2:
MTU2S: Multi-function timer pulse unit 2 (subset)
POE:
SCI:
SCIF:
SSU:
I
CMT:
ADC:
2
C2:
WDT
DTC
Multi-function timer pulse unit 2
Serial communication interface
Pin function controller
Serial communication interface with FIFO
Data transfer controller
Synchronous serial communication unit
Port output enable
Compare match timer
A/D converter
I
2
CPG
C bus interface 2
Internal bus
controller
AUD
*
2
MTU2
DMAC
Rev. 3.00 May 17, 2007 Page 7 of 1582
Peripheral bus (Pφ)
MTU2S
I bus (Bφ)
L bus (Iφ)
POE
SSU
Section 1 Overview
REJ09B0181-0300
I
2
C2
ADC