DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 470

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 10 Direct Memory Access Controller (DMAC)
• Burst Mode
Figure 10.12 shows DMA transfer timing in burst mode.
Rev. 3.00 May 17, 2007 Page 412 of 1582
REJ09B0181-0300
In burst mode, once the DMAC obtains the bus mastership, the transfer is performed
continuously without releasing the bus mastership until the transfer end condition is satisfied.
In external request mode with level detection of the DREQ pin, however, when the DREQ pin
is not active, the bus mastership passes to the other bus master after the DMAC transfer
request that has already been accepted ends, even if the transfer end conditions have not been
satisfied.
Bus cycle
DREQ
Figure 10.12 DMA Transfer Example in Burst Mode
CPU
(Dual Address, DREQ Low Level Detection)
CPU
CPU
DMAC DMAC DMAC
Read
Write
Read
DMAC DMAC
Write
Read
DMAC
Write
CPU