DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 191

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

6.8.1
1. Do not select DMAC activation sources.
2. For DTC, set the corresponding DTCE bits and DISEL bits to 1.
3. When an interrupt occurs, an activation request is sent to the DTC.
4. When completing a data transfer, the DTC clears the DTCE bit to 0 and sends an interrupt
5. The CPU clears the interrupt source in the interrupt handling routine then checks the transfer
Interrupt source
Interrupt source
flag clear
request to the CPU. The activation source is not cleared.
counter value. When the transfer counter value is not 0, the CPU sets the DTCE bit to 1 and
allows the next data transfer. If the transfer counter value = 0, the CPU performs the necessary
end processing in the interrupt processing routine.
Handling Interrupt Request Signals as Sources for DTC Activation and CPU
Interrupts, but Not DMAC Activation
Figure 6.6 On-Chip Module Interrupt Control Block Diagram
Interrupt source flag clear by DTC
DTCER
DTCE clear
Interrupt controller
Interrupt priority
determination
Rev. 3.00 May 17, 2007 Page 133 of 1582
DTC activation
request
DTCECLR
Transfer end
Section 6 Interrupt Controller (INTC)
Decode
DTC
Interrupt request to CPU
DMAC
DMAC activation
request
Interrupt source
flag clear
by DMAC
REJ09B0181-0300
CHCR
RS bits 3 to 0