DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 481

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

10.5.10 Number of Cycles per Access to On-Chip RAM by DMAC
The number of cycles required for read/write access to on-chip RAM from the DMAC is as shown
in table 10.9, which differs depending on the frequency ratio of Iφ (internal clock) to Bφ (external
bus clock).
Table 10.9 Number of Cycles per Access to On-Chip RAM by DMAC
Notes: 1. Bcyc is the external bus clock cycle.
10.5.11 Note on DMAC Transfer in Burst Mode when Activation Source is MTU2
The corresponding bit among DMMTU4 to DMMTU0 in the bus function extending register
(BSCEHR) must be set when performing DMA transfer in burst mode with the MTU2 specified as
the activation source. For details, see section 9.4.8, Bus Function Extending Register (BSCEHR).
10.5.12 Bus Function Extending Register (BSCEHR)
With the bus function extending register (BSCEHR), it is possible to set the function to perform
transfer by the DMAC preferentially. For details, see section 9.4.8, Bus Function Extending
Register (BSCEHR).
Setting of Iφ:Bφ
1:1
1:1/2
1:1/3
1:1/4 or less
2. The number of cycles for access to the on-chip peripheral I/O or an external device are
indicated in section 9.5.16, Access to On-Chip Peripheral I/O Registers by CPU, and
section 9.5.17, Access to External Memory by CPU. The access cycles are obtained by
subtracting the cycles of Iφ required for L-bus access from the cycles required for
access by the CPU.
Read
3 × Bcyc
2 × Bcyc
2 × Bcyc
1 × Bcyc
Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 May 17, 2007 Page 423 of 1582
Write
3 × Bcyc
1 × Bcyc
1 × Bcyc
1 × Bcyc
REJ09B0181-0300