DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 513

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 11.22 TIOR_1 (Channel 1)
[Legend]
x:
Note:
Bit 3
IOA3
0
1
Don't care
*
Bit 2
IOA2
1
0
1
0
After power-on reset, 0 is output until TIOR is set.
Bit 1
IOA1
0
1
0
1
0
1
x
Bit 0
IOA0
0
1
0
1
0
1
0
1
0
1
x
x
TGRA_1
Function
Output
compare
register
Input capture
register
TIOC1A Pin Function
Output retained*
Initial output is 0
0 output at compare match
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
Output retained
Initial output is 1
0 output at compare match
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of channel 0/TGRA_0
compare match/input capture
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 3.00 May 17, 2007 Page 455 of 1582
Description
REJ09B0181-0300

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