DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 963

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18.3
The I
states during each processing, refer to section 27, List of Registers.
Table 18.2 Register Configuration
18.3.1
ICCR1 is an 8-bit readable/writable register that enables or disables the I
controls transmission or reception, and selects master or slave mode, transmission or reception,
and transfer clock frequency in master mode.
Bit
7
Register Name
I
I
I
I
register
I
I
I
I
NF2CYC register
2
2
2
2
2
2
2
2
C bus control register 1
C bus control register 2
C bus mode register
C bus interrupt enable
C bus status register
C bus slave address register
C bus transmit data register
C bus receive data register
2
C bus interface 2 has the following registers. For details on register addresses and register
Register Descriptions
I
2
Bit Name
ICE
C Bus Control Register 1 (ICCR1)
Initial value:
Initial
Value
0
R/W:
Bit:
R/W
ICE
Abbrevia-
tion
ICCR1
ICCR2
ICMR
ICIER
ICSR
SAR
ICDRT
NF2CYC
ICDRR
7
0
R/W
R/W
RCVD
R/W
6
0
R/W
MST
Description
I
0: This module is halted.
1: This bit is enabled for transfer operations. (SCL and
2
5
0
C Bus Interface 2 Enable
SDA pins are bus drive state.)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TRS
4
0
Initial value
H'00
H'7D
H'38
H'00
H'00
H'00
H'FF
H'00
H'FF
R/W
3
0
Rev. 3.00 May 17, 2007 Page 905 of 1582
R/W
2
0
CKS[3:0]
Section 18 I
R/W
1
0
Address
H'FFFFCD80
H'FFFFCD81
H'FFFFCD82
H'FFFFCD83
H'FFFFCD84
H'FFFFCD85
H'FFFFCD86
H'FFFFCD87
H'FFFFCD88
R/W
2
C bus interface 2,
0
0
2
C Bus Interface 2 (I
REJ09B0181-0300
Access Size
8
8
8
8
8
8
8
8
8
2
C2)