DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 959

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The I
interface functions. However, the configuration of the registers that control the I
partly from the Philips register configuration.
Figure 18.1 shows a block diagram of the I
I/O pin connections to external circuits.
18.1
• Selection of I
• Continuous transmission/reception
• Module standby mode can be set
I
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization function
• Six interrupt sources
• Direct bus drive
2
C bus format:
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically.
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
The data transfer controller (DTC) can be activated by a transmit-data-empty request or
receive-data-full request to transfer data.
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
2
C bus interface 2 conforms to and provides a subset of the Philips I
Features
2
C format or clock synchronous serial format
Section 18 I
2
C Bus Interface 2 (I
2
C bus interface 2. Figure 18.2 shows an example of
Rev. 3.00 May 17, 2007 Page 901 of 1582
Section 18 I
2
2
C (Inter-IC) bus
C2)
2
C Bus Interface 2 (I
2
C bus differs
REJ09B0181-0300
2
C2)