DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1405

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Register Name
Serial mode register_3
Bit rate register_3
Serial control register_3
Transmit FIFO data register_3
Serial status register_3
Receive FIFO data register_3
FIFO control register_3
FIFO data count register_3
Serial port register_3
Line status register_3
Timer control register_3
Timer control register_4
Timer mode register_3
Timer mode register_4
Timer I/O control register H_3
Timer I/O control register L_3
Timer I/O control register H_4
Timer I/O control register L_4
Timer interrupt enable register_3
Timer interrupt enable register_4
Timer output master enable register
Timer gate control register
Timer output control register 1
Timer output control register 2
Timer counter_3
Timer counter_4
Timer cycle data register
Timer dead time data register
Timer general register A_3
Timer general register B_3
Timer general register A_4
Abbreviation
SCSMR_3
SCBRR_3
SCSCR_3
SCFTDR_3
SCFSR_3
SCFCR_3
SCFDR_3
SCSPTR_3
SCLSR_3
TCR_3
TCR_4
TMDR_3
TMDR_4
TIORH_3
TIORL_3
TIORH_4
TIORL_4
TIER_3
TIER_4
TOER
TGCR
TOCR1
TOCR2
TCNT_3
TCNT_4
TCDR
TDDR
TGRA_3
TGRB_3
TGRA_4
SCFRDR_3
No. of
Bits
16
8
16
8
16
8
16
16
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
16
16
Address
H'FFFFC180
H'FFFFC182
H'FFFFC184
H'FFFFC186
H'FFFFC188
H'FFFFC18A
H'FFFFC18C
H'FFFFC18E
H'FFFFC190
H'FFFFC192
H'FFFFC200
H'FFFFC201
H'FFFFC202
H'FFFFC203
H'FFFFC204
H'FFFFC205
H'FFFFC206
H'FFFFC207
H'FFFFC208
H'FFFFC209
H'FFFFC20A
H'FFFFC20D
H'FFFFC20E
H'FFFFC20F
H'FFFFC210
H'FFFFC212
H'FFFFC214
H'FFFFC216
H'FFFFC218
H'FFFFC21A
H'FFFFC21C
Module
SCIF
(Channel 3)
MTU2
Rev. 3.00 May 17, 2007 Page 1347 of 1582
Access
Size
16
8
16
8
16
8
16
16
16
16
8, 16, 32
8
8, 16
8
8, 16, 32
8
8, 16
8
8, 16
8
8
8
8, 16
8
16, 32
16
16, 32
16
16, 32
16
16, 32
Section 27 List of Registers
No. of Access
States
Pφ reference
B:2
W:2
MPφ reference
B:2
W:2
L:4
REJ09B0181-0300
Connected Bus
Width
16 bits
16 bits