DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1612

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Rev. 3.00 May 17, 2007 Page 1554 of 1582
REJ09B0181-0300
Item
16.3.7 Serial Status Register
(SCFSR)
Figure 16.13 Sample Flowchart for
Transmitting Serial Data
Page Revision (See Manual for Details)
805,
809
845
Amended
Amended
Bit
5
0
Bit Name Description
TDFE
DR
Write transmit data to SCFTDR
and TEND flag in SCFSR to 0
Read TDFE flag in SCFSR
after reading them as 1
and clear TDFE flag
Start of transmission
TDFE = 1?
Yes
Transmit FIFO Data Empty
….
1: The number of transmit data in SCFTDR is less
[Setting conditions]
•
•
Receive Data Ready
….
[Clearing conditions]
•
•
•
than or equal to the specified transmission
trigger number*
TDFE is set to 1 by a power-on reset
TDFE is set to 1 when the number of transmit
data in SCFTDR becomes less than or equal
to the specified transmission trigger number
as a result of transmission
DR is cleared to 0 when the chip undergoes a
power-on reset
DR is cleared to 0 when all receive data are
read after 1 is read from DR and then 0 is
written
DR is cleared to 0 when all receive data in
SCFRDR are read by the DTC
No
[1]
[1] SCIF status check and transmit data
[2] Serial transmission continuation
write:
TDFE flag and the TEND flag are set
to 1, then write transmit data to
SCFTDR, and clear the TDFE flag
and the TEND flag to 0.
procedure:
1 from the TDFE flag to confirm that
writing is possible, them write data to
SCFTDR, and then clear the TDFE
flag to 0.
Read SCFSR and check that the
To continue serial transmission, read