DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 577
DF70845AD80FPV
Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet
1.DF70844AD80FPV.pdf
(1644 pages)
Specifications of DF70845AD80FPV
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 577 of 1644
- Download datasheet (10Mb)
Input Capture Function:
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge.
Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1,
it is also possible to specify another channel's counter input clock or compare match signal as the
input capture source.
Note: When another channel's counter input clock is used as the input capture input for channels
1. Example of Input Capture Operation Setting Procedure
Figure 11.10 shows an example of the input capture operation setting procedure.
0 and 1, MPφ/1 should not be selected as the counter input clock used for input capture
input. Input capture will not be generated if MPφ/1 is selected.
Figure 11.10 Example of Input Capture Operation Setting Procedure
<Input capture operation>
Select input capture input
Input selection
Start count
[1]
[2]
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
[1] Designate TGR as an input capture
[2] Set the CST bit in TSTR to 1 to start
register by means of TIOR, and select
rising edge, falling edge, or both edges
as the input capture source and input
signal edge.
the count operation.
Rev. 3.00 May 17, 2007 Page 519 of 1582
REJ09B0181-0300
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