DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 913

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16.7.3
Break signals can be detected by reading the RXD pin directly when a framing error (FER) is
detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set
and the parity error flag (PER) may also be set. Note that, although transfer of receive data to
SCFRDR is halted in the break state, the SCIF receiver continues to operate.
16.7.4
The I/O condition and level of the TXD pin are determined by the SPBIO and SPBDT bits in the
serial port register (SCSPTR). This feature can be used to send a break signal.
Until TE bit is set to 1 (enabling transmission) after initializing, TXD pin does not work. During
the period, mark status is performed by SPBDT bit. Therefore, the SPBIO and SPBDT bits should
be set to 1 (high level output).
To send a break signal during serial transmission, clear the SPBDT bit to 0 (designating low
level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized regardless of the current transmission state, and 0 is output from the TXD
pin.
16.7.5
The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the
SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock.
Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in
figure 16.23.
Break Detection and Processing
Sending a Break Signal
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)
Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 May 17, 2007 Page 855 of 1582
REJ09B0181-0300