DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1383

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a
32-bit data bus (L bus), and to the direct memory access controller (DMAC), and data transfer
controller (DTC) by a 32-bit data bus (I bus), enabling 8, 16, or 32-bit width access to data in the
on-chip RAM.
The on-chip RAM is allocated to different addresses according to each product as shown in figure
25.1, and the on-chip RAM is divided into page 0 and page 1 based on the addresses. The on-chip
RAM can be accessed from the CPU (via the L bus) and the DMAC/DTC (via the I bus). When
different buses request to access the same page simultaneously, the priority becomes I bus
(DMAC/DTC) > L bus (CPU). Since such kind of conflict degrades the RAM access performance,
software should be created so as to avoid conflicts. For example, conflict does not occur when the
buses access different pages. An access from the L bus (CPU) is a 1-cycle access as long as page
conflict does not occur. The number of bus cycles in accesses from the I bus (DMAC/DTC) differ
depending on the ratio between the internal clock (Iφ) and bus clock (Bφ), and the operating state
of the DMAC/DTC. The contents of the on-chip RAM are retained in sleep mode or software
standby mode, and at a power-on reset or manual reset. However, the contents of the on-chip
RAM are not retained in deep software standby mode.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the RAM control
register (RAMCR). For details on the RAM control register (RAMCR), refer to section 26.3.7,
RAM Control Register (RAMCR).
RAM0200A_010020030800
H'FFFFBFFF
H'FFFF9FFF
H'FFFFA000
H'FFFF8000
(256-kbyte flash memory version)
SH7083/SH7084/SH7085
(16 kbytes)
8 kbytes
8 kbytes
Page 0
Page 1
Figure 25.1 On-chip RAM Addresses
Section 25 RAM
H'FFFFBFFF
H'FFFF9FFF
H'FFFFA000
H'FFFF4000
(512-kbyte flash memory version)/
Rev. 3.00 May 17, 2007 Page 1325 of 1582
SH7083/SH7084/SH7085
(32 kbytes)
24 kbytes
8 kbytes
SH7086
Page 0
Page 1
REJ09B0181-0300
Section 25 RAM