DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 301

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
5
4
3, 2
1
Bit Name
DMAIWA


HIZMEM
Initial
Value
0
1
All 0
0
R/W
R/W
R
R
R/W
Description
Specification for Method of Inserting Wait States
between Access Cycles during DMA Single Address
Transfer
Specifies the method of inserting the idle cycles
specified by the DMAIW1 and DMAIW0 bits. Clearing
this bit will make this LSI insert the idle cycles when
another device, which includes this LSI, drives the data
bus after an external device with DACK drove it. When
the external device with DACK drives the data bus
continuously, idle cycles are not inserted. Setting this bit
will make this LSI insert the idle cycles after one access
is completed even when the continuous accesses to an
external device with DACK are performed.
0: Idle cycles are inserted when another device drives
1: Idle cycles are always inserted after external device
Reserved
This bit is always read as 1. The write value should
always be 1.
Reserved
These bits are always read as 0. The write value should
always be 0.
High-Z Memory Control
Specifies the pin state in software standby mode for
A29 to A0, BS, CSn, RDWR, WRxx, RD, AH, FRAME,
ICIORD, ICIOWR, WE, CE1A, CE1B, CE2A, and
CE2B. While the bus is released, these pins are in high-
impedance state regardless of this bit setting.
0: High impedance in software standby mode
1: Driven in software standby mode
data bus after external device with DACK drives data
bus
with DACK is accessed.
Rev. 3.00 May 17, 2007 Page 243 of 1582
Section 9 Bus State Controller (BSC)
REJ09B0181-0300