DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 924

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 17 Synchronous Serial Communication Unit (SSU)
17.3.3
SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous
serial communication.
Rev. 3.00 May 17, 2007 Page 866 of 1582
REJ09B0181-0300
Bit
1, 0
Bit
7
6
5
Bit Name
DATS[1:0] 00
Bit Name
MLS
CPOS
CPHS
SS Mode Register (SSMR)
Initial
Value
Initial
Value
0
0
Initial value:
0
R/W:
Bit:
R/W
MLS
R/W
R/W
R/W
R/W
R/W
R/W
7
0
CPOS CPHS
R/W
6
0
Description
Transmit/Receive Data Length Select
Select serial data length.
00: 8 bits
01: 16 bits
10: 32 bits
11: Setting prohibited
Description
MSB First/LSB First Select
Selects that the serial data is transmitted in MSB first or
LSB first.
0: LSB first
1: MSB first
Clock Polarity Select
Selects the SSCK clock polarity.
0: High output in idle mode, and low output in active
1: Low output in idle mode, and high output in active
Clock Phase Select (Only for SSU Mode)
Selects the SSCK clock phase.
0: Data changes at the first edge.
1: Data is latched at the first edge.
R/W
5
0
mode
mode
R
4
0
-
R
3
0
-
R/W
2
0
CKS[2:0]
R/W
1
0
R/W
0
0