DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 16

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

11.4 Operation ........................................................................................................................... 515
11.5 Interrupt Sources................................................................................................................ 605
11.6 Operation Timing............................................................................................................... 610
11.7 Usage Notes ....................................................................................................................... 623
Rev. 3.00 May 17, 2007 Page xvi of lviii
11.3.17 Timer Counter Synchronous Start Register (TCSYSTR) ..................................... 490
11.3.18 Timer Read/Write Enable Register (TRWER) ..................................................... 493
11.3.19 Timer Output Master Enable Register (TOER) .................................................... 494
11.3.20 Timer Output Control Register 1 (TOCR1).......................................................... 495
11.3.21 Timer Output Control Register 2 (TOCR2).......................................................... 498
11.3.22 Timer Output Level Buffer Register (TOLBR) .................................................... 501
11.3.23 Timer Gate Control Register (TGCR) .................................................................. 502
11.3.24 Timer Subcounter (TCNTS) ................................................................................. 504
11.3.25 Timer Dead Time Data Register (TDDR)............................................................. 505
11.3.26 Timer Cycle Data Register (TCDR) ..................................................................... 505
11.3.27 Timer Cycle Buffer Register (TCBR)................................................................... 506
11.3.28 Timer Interrupt Skipping Set Register (TITCR)................................................... 506
11.3.29 Timer Interrupt Skipping Counter (TITCNT)....................................................... 508
11.3.30 Timer Buffer Transfer Set Register (TBTER) ...................................................... 509
11.3.31 Timer Dead Time Enable Register (TDER) ......................................................... 511
11.3.32 Timer Waveform Control Register (TWCR) ........................................................ 512
11.3.33 Bus Master Interface............................................................................................. 514
11.4.1 Basic Functions..................................................................................................... 515
11.4.2 Synchronous Operation......................................................................................... 521
11.4.3 Buffer Operation................................................................................................... 523
11.4.4 Cascaded Operation .............................................................................................. 527
11.4.5 PWM Modes......................................................................................................... 532
11.4.6 Phase Counting Mode........................................................................................... 537
11.4.7 Reset-Synchronized PWM Mode ......................................................................... 544
11.4.8 Complementary PWM Mode................................................................................ 547
11.4.9 A/D Converter Start Request Delaying Function.................................................. 591
11.4.10 MTU2–MTU2S Synchronous Operation.............................................................. 595
11.4.11 External Pulse Width Measurement...................................................................... 601
11.4.12 Dead Time Compensation .................................................................................... 602
11.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 604
11.5.1 Interrupt Sources and Priorities ............................................................................ 605
11.5.2 DTC/DMAC Activation ....................................................................................... 607
11.5.3 A/D Converter Activation..................................................................................... 608
11.6.1 Input/Output Timing............................................................................................. 610
11.6.2 Interrupt Signal Timing ........................................................................................ 617
11.7.1 Module Standby Mode Setting ............................................................................. 623