DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 22

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

19.4 Operation ........................................................................................................................... 962
19.5 Interrupt Sources and DMAC and DTC Transfer Requests............................................... 968
19.6 Definitions of A/D Conversion Accuracy.......................................................................... 969
19.7 Usage Notes ....................................................................................................................... 972
Section 20 Compare Match Timer (CMT) ........................................................ 975
20.1 Features.............................................................................................................................. 975
20.2 Register Descriptions......................................................................................................... 976
20.3 Operation ........................................................................................................................... 980
20.4 Interrupts............................................................................................................................ 981
20.5 Usage Notes ....................................................................................................................... 982
Rev. 3.00 May 17, 2007 Page xxii of lviii
19.3.4 A/D Trigger Select Registers_0 and _1 (ADTSR_0 and ADTSR_1) ................... 956
19.4.1 Single Mode.......................................................................................................... 962
19.4.2 Continuous Scan Mode......................................................................................... 962
19.4.3 Single-Cycle Scan Mode ...................................................................................... 963
19.4.4 Input Sampling and A/D Conversion Time .......................................................... 963
19.4.5 A/D Converter Activation by MTU2 or MTU2S.................................................. 966
19.4.6 External Trigger Input Timing.............................................................................. 966
19.4.7 2-Channel Scanning.............................................................................................. 967
19.7.1 Module Standby Mode Setting ............................................................................. 972
19.7.2 Permissible Signal Source Impedance .................................................................. 972
19.7.3 Influences on Absolute Accuracy ......................................................................... 972
19.7.4 Range of Analog Power Supply and Other Pin Settings....................................... 973
19.7.5 Notes on Board Design ......................................................................................... 973
19.7.6 Notes on Noise Countermeasures ......................................................................... 974
20.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 977
20.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 977
20.2.3 Compare Match Counter (CMCNT)..................................................................... 979
20.2.4 Compare Match Constant Register (CMCOR) ..................................................... 979
20.3.1 Interval Count Operation ...................................................................................... 980
20.3.2 CMCNT Count Timing......................................................................................... 980
20.4.1 CMT Interrupt Sources and DTC Activation........................................................ 981
20.4.2 Timing of Setting Compare Match Flag ............................................................... 981
20.4.3 Timing of Clearing Compare Match Flag............................................................. 981
20.5.1 Module Standby Mode Setting ............................................................................. 982
20.5.2 Conflict between Write and Compare-Match Processes of CMCNT ................... 982
20.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 983
20.5.4 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 984
20.5.5 Compare Match between CMCNT and CMCOR ................................................. 984