DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 381

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Single Write: A write access ends in one cycle when the data bus width is larger than or equal to
access size. This is called single write.
Figure 9.21 shows the single write basic timing.
Bank Active: The SDRAM bank function is used to support high-speed accesses to the same row
address. When the BACTV bit in SDCR is 1, accesses are performed using commands without
auto-precharge (READ or WRIT). This function is called bank-active function. This function is
valid only for area 3. When area 3 is set to bank-active mode, area 2 should be set to normal space
or SRAM with byte selection. When areas 2 and 3 are both set to SDRAM, auto-precharge mode
must be set.
In this case, precharging is not performed when the access ends. When accessing the same row
address in the same bank, it is possible to issue the READ or WRIT command immediately,
without issuing an ACTV command. As SDRAM is internally divided into several banks, it is
possible to activate one row address in each bank. If the next access is to a different row address, a
PRE command is first issued to precharge the relevant bank, then when precharging is completed,
Figure 9.21 Single Write Basic Timing (Auto-Precharge)
RASL, RASU
CASL, CASU
Notes: 1.
A12/A11*
D31 to D0
A25 to A0
DACKn*
DQMxx
RDWR
2.
CSn
CK
BS
1
2
Address pin to be connected to pin A10 of SDRAM.
The waveform for DACKn is when active low is specified.
Tr
Tc1
Trwl
Rev. 3.00 May 17, 2007 Page 323 of 1582
Tap
Section 9 Bus State Controller (BSC)
REJ09B0181-0300