DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 340

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Rev. 3.00 May 17, 2007 Page 282 of 1582
REJ09B0181-0300
Bit
9
8
7 to 5
Bit Name
CSSTP3
DTPR

Initial
Value
0
0
All 0
R/W
R/W
R/W
R
Description
Select Priority for External Memory Access by CPU
Specifies whether or not access to the external space by
the CPU takes priority over DTC or DMAC transfer in
cycle-steal mode.
0: DMAC transfer and DTC transfer have priority.
1: External space access from the CPU has priority.
Note: When this bit is 0, and access to internal I/O from
Application of Priority in DTC Activation
When multiple DTC activation requests are generated
before the DTC is activated, specify whether transfer
starts from the first request to have been generated or is
in accord with the priority order for DTC activation
requests.
However, when multiple DTC activation requests have
been issued while the DTC is active, the next transfer to
be triggered will be that with the highest DTC activation
priority.
0: Start transfer in response to the first request to have
1: Start transfer in accord with DTC activation request
Notes: When this bit is set to 1, the following restrictions
Reserved
These bits are always read as 0. The write value should
always be 0.
been generated.
priority.
the CPU is immediately followed by access to
external space from the CPU, a NOP 1Bφ in
duration is inserted between the two access
cycles.
apply.
1. The vector information must be in on-chip ROM
2. The transfer information must be in on-chip
3. Skipping of transfer information reading is
or on-chip RAM.
RAM.
always disabled.