DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 242

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 8 Data Transfer Controller (DTC)
8.3
The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC
activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt
source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer
(or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or
corresponding DTCER bit is cleared.
8.4
Locate the transfer information in the data area. The start address of transfer information should be
located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored
during access ([1:0] = B'00.) Transfer information located in the data area is shown in figure 8.2.
Only in the case where all transfer sources/transfer destinations are in on-chip RAM and on-chip
peripheral modules, short address mode can be selected by setting the DTSA bit in the bus
function extending register (BSCEHR) to 1 (see section 9.4.8, Bus Function Extending Register
(BSCEHR)).
Normally, four longwords of transfer information has to be read. But if short address mode is
selected, the size of transfer information is reduced to three longwords, which can shorten the
period over which the DTC is active.
The DTC reads the start address of the transfer information from the vector table for every
activation source and reads the transfer information from this start address. Figure 8.3 shows
correspondences between the DTC vector table and transfer information.
Rev. 3.00 May 17, 2007 Page 184 of 1582
REJ09B0181-0300
Activation Sources
Location of Transfer Information and DTC Vector Table