DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 238

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 8 Data Transfer Controller (DTC)
8.2.7
DTCER which is comprised of eight registers, DTCERA to DTCERE, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 8.2.
Initial value:
Rev. 3.00 May 17, 2007 Page 180 of 1582
REJ09B0181-0300
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W:
Bit:
DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10
Bit Name
DTCE15
DTCE14
DTCE13
DTCE12
DTCE11
DTCE10
DTCE9
DTCE8
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
R/W
DTC Enable Registers A to E (DTCERA to DTCERE)
15
0
R/W
14
0
R/W
13
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
12
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11
0
R/W
10
0
Description
DTC Activation Enable 15 to 0
If set to 1, the corresponding interrupt source is specified
as a DTC activation source.
[Clearing conditions]
•
•
•
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not ended
[Setting condition]
•
DTCE9
R/W
9
0
Writing 0 to the bit after reading 1 from it
When the DISEL bit is 1 and the data transfer has
ended
When the specified number of transfers have ended
Writing 1 to the bit after reading 0 from it
DTCE8
R/W
8
0
DTCE7
R/W
7
0
DTCE6
R/W
6
0
DTCE5
R/W
5
0
DTCE4
R/W
4
0
DTCE3
R/W
3
0
DTCE2
R/W
2
0
DTCE1
R/W
1
0
DTCE0
R/W
0
0