DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 942

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 17 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 May 17, 2007 Page 884 of 1582
REJ09B0181-0300
User operation
User operation
User operation
(1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0
(2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0
(3) When 32-bit data length is selected (SSTDR0 to SSTDR3 are valid) with CPOS = 0 and CPHS = 0
LSI operation
LSI operation
LSI operation
(MSB first)
(MSB first)
(LSB first)
(LSB first)
SSCK
TDRE
TEND
SSCK
TDRE
TEND
SSCK
TDRE
TEND
SCS
SSO
SCS
SSO
SSO
SCS
SSO
SSO
Figure 17.5 Example of Transmission Operation (SSU Mode)
Data written to SSTDR0 to SSTDR3
Data written to SSTDR0
Data written to SSTDR0 and SSTDR1
TXI interrupt
generated
Bit
Bit
Bit
Bit
Bit
0
0
7
0
7
SSTDR 3
SSTDR0
Bit
Bit
Bit
(LSB first transmission)
to
to
1
1
6
Bit
Bit
Bit
Bit
Bit
5
2
2
7
0
1 frame
SSTDR1
SSTDR0
SSTDR0
Bit
Bit
Bit
Bit
Bit
3
3
4
0
7
SSTDR2
SSTDR1
Bit
Bit
Bit
to
to
4
4
3
TXI interrupt generated
1 frame
TEI interrupt
Bit
Bit
Bit
Bit
Bit
5
5
2
7
0
generated
Bit
Bit
Bit
Bit
Bit
6
6
1
0
7
SSTDR1
SSTDR2
1 frame
TXI interrupt generated
Bit
Bit
Bit
to
to
7
7
0
Bit
Bit
Bit
Bit
0
7
0
7
Data written to SSTDR0
TXI interrupt
Bit
Bit
Bit
Bit
1
6
0
7
generated
SSTDR0
SSTDR3
Bit
Bit
Bit
7
2
to
to
5
SSTDR0
SSTDR1
TEI interrupt generated
(MSB first transmission)
Bit
Bit
Bit
Bit
Bit
6
3
4
7
0
Bit
Bit
Bit
5
4
3
SSTDR0
1 frame
Bit
Bit
Bit
4
5
2
TEI interrupt generated
Bit
Bit
Bit
3
6
1
Bit
Bit
Bit
2
7
0
TEI interrupt
generated
Bit
1
Bit
0