DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 330

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
9.4.4
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
Initial value:
Initial value:
Rev. 3.00 May 17, 2007 Page 272 of 1582
REJ09B0181-0300
Bit
31 to 21
20, 19
18
17, 16
R/W:
R/W:
Bit:
Bit:
SDRAM Control Register (SDCR)
31
15
R
R
0
0
Bit Name

A2ROW[1:0] 00

A2COL[1:0]
-
-
30
14
R
R
0
0
-
-
29
13
R
R
0
0
-
-
Initial
Value
All 0
0
00
28
12
R
R
0
0
-
-
RFSH RMODE
R/W
27
11
R
0
0
-
R/W
R
R/W
R
R/W
R/W
26
10
R
0
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Bits of Row Address for Area 2
Specify the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
Reserved
This bit is always read as 0. The write value should
always be 0.
Number of Bits of Column Address for Area 2
Specify the number of bits of column address for area
2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
25
R
R
0
9
0
-
-
BACTV
R/W
24
R
0
8
0
-
23
R
R
0
7
0
-
-
22
R
R
0
6
0
-
-
21
R
R
0
5
0
-
-
A2ROW[1:0]
R/W
R/W
A3ROW[1:0]
20
0
4
0
R/W
R/W
19
0
3
0
18
R
R
0
2
0
-
-
R/W
R/W
A2COL[1:0]
A3COL[1:0]
17
0
1
0
R/W
R/W
16
0
0
0