DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 109

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note:
Instruction
STS
STS
STS
STS.L MACH,@–Rn
STS.L MACL,@–Rn
STS.L PR,@–Rn
TRAPA #imm
MACH,Rn
MACL,Rn
PR,Rn
*
Number of execution cycles until this LSI enters sleep mode.
About the number of execution cycles:
The table lists the minimum number of execution cycles. In practice, the number of
execution cycles will be increased depending on the conditions such as:
When there is a conflict between instruction fetch and data access
When the destination register of a load instruction (memory → register) is also used
by the instruction immediately after the load instruction.
Operation
MACH → Rn
MACL → Rn
PR → Rn
Rn–4 → Rn, MACH → (Rn) 0100nnnn00000010
Rn–4 → Rn, MACL → (Rn) 0100nnnn00010010
Rn–4 → Rn, PR → (Rn)
PC/SR → Stack area,
(imm × 4 + VBR) → PC
Code
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00100010
11000011iiiiiiii
Rev. 3.00 May 17, 2007 Page 51 of 1582
Execution
Cycles
1
1
1
1
1
1
8
REJ09B0181-0300
Section 2 CPU
T Bit

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