DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 479

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

10.5
10.5.1
When burst mode and cycle steal mode are specified in multiple channels at the same time,
unnecessary DACK may be asserted at the end of burst transfer if the following conditions are all
satisfied.
1. When DMA transfer is performed with burst mode and cycle steal mode being specified in
2. When dual address mode is specified for the channel used in burst mode and DACK output is
3. When the DMAC cannot acquire the bus mastership after the end of burst transfer while the
This can be avoided by one of the following actions.
Action 1: After confirming the end of burst transfer (TE bit = 1), perform remaining DMA transfer
Action 2: Do not enable DACK in write cycles for the channel used in burst mode.
Action 3: When performing DMA transfer in multiple channels at the same time, select either
10.5.2
During DMA transfer by peripheral modules, do not set the clock ratio of bus clock
(Bφ):peripheral clock (Pφ), bus clock (Bφ):MTU2 clock (MPφ), and bus clock (Bφ):MTU2S clock
(MIφ) to 1:1/3 or 1:1/4
10.5.3
DMAC operation can be enabled or disabled by setting the standby control register. The DMAC is
disabled by default. After module standby mode is canceled, access to the DMAC registers is
enabled.
Note that software standby mode or module standby mode must not be entered while the DMAC
is operating. Before entering software standby mode or module standby mode, clear the DE bits in
all channels. For details, refer to section 26, Power-Down Modes.
multiple channels at the same time.
enabled in write cycles.
DMAC has accepted a cycle-steal transfer request.
Usage Notes
Notes on Output from DACK Pin
DMA Transfer by Peripheral Modules
Module Standby Mode Setting
in cycle steal mode.
burst mode or cycle steal mode for all channels.
Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 May 17, 2007 Page 421 of 1582
REJ09B0181-0300